Novel nanocomposite-superlattices for low energy and high stability nanoscale phase-change memory.

Data-centric applications are pushing the limits of energy-efficiency in today's computing systems, including those based on phase-change memory (PCM). This technology must achieve low-power and stable operation at nanoscale dimensions to succeed in high-density memory arrays. Here we use a novel combination of phase-change material superlattices and nanocomposites (based on Ge4Sb6Te7), to achieve record-low power density ≈ 5 MW/cm2 and ≈ 0.7 V switching voltage (compatible with modern logic processors) in PCM devices with the smallest dimensions to date (≈ 40 nm) for a superlattice technology on a CMOS-compatible substrate. These devices also simultaneously exhibit low resistance drift with 8 resistance states, good endurance (≈ 2 × 108 cycles), and fast switching (≈ 40 ns). The efficient switching is enabled by strong heat confinement within the superlattice materials and the nanoscale device dimensions. The microstructural properties of the Ge4Sb6Te7 nanocomposite and its high crystallization temperature ensure the fast-switching speed and stability in our superlattice PCM devices. These results re-establish PCM technology as one of the frontrunners for energy-efficient data storage and computing.

High-performance monolayer MoS2nanosheet GAA transistor.

In this article, a 0.7 nm thick monolayer MoS2nanosheet gate-all-around field effect transistors (NS-GAAFETs) with conformal high-κmetal gate deposition are demonstrated. The device with 40 nm channel length exhibits a high on-state current density of ~410µAµm-1with a large on/off ratio of 6 × 108at drain voltage = 1 V. The extracted contact resistance is 0.48 ± 0.1 kΩµm in monolayer MoS2NS-GAAFETs, thereby showing the channel-dominated performance with the channel length scaling from 80 to 40 nm. The successful demonstration of device performance in this work verifies the integration potential of transition metal dichalcogenides for future logic transistor applications.

Sub-Nanometer Interfacial Oxides on Highly Oriented Pyrolytic Graphite and Carbon Nanotubes Enabled by Lateral Oxide Growth.

A new generation of compact and high-speed electronic devices, based on carbon, would be enabled through the development of robust gate oxides with sub-nanometer effective oxide thickness (EOT) on carbon nanotubes or graphene nanoribbons. However, to date, the lack of dangling bonds on sp2 oriented graphene sheets has limited the high precursor nucleation density enabling atomic layer deposition of sub-1 nm EOT gate oxides. It is shown here that by deploying a low-temperature AlOx (LT AlOx) process, involving atomic layer deposition (ALD) of Al2O3 at 50 °C with a chemical vapor deposition (CVD) component, a high nucleation density layer can be formed, which templates the growth of a high-k dielectric, such as HfO2. Atomic force microscopy (AFM) imaging shows that at 50 °C, the Al2O3 spontaneously forms a pinhole-free, sub-2 nm layer on graphene. Density functional theory (DFT) based simulations indicate that the spreading out of AlOx clusters on the carbon surface enables conformal oxide deposition. Device applications of the LT AlOx deposition scheme were investigated through electrical measurements on metal oxide semiconductor capacitors (MOSCAPs) with Al2O3/HfO2 bilayer gate oxides using both standard Ti/Pt metal gates as well as TiN/Ti/Pd gettering gates. In this study, LT AlOx was used to nucleate HfO2 and it was shown that bilayer gate oxide stacks of 2.85 and 3.15 nm were able to achieve continuous coverage on carbon nanotubes (CNTs). The robustness of the bilayer was tested through deployment in a CNT-based field-effect transistor (FET) configuration with a gate leakage of less than 10-8 A/µm per CNT.